1. Field of the Invention
The present invention relates to the field of integrated circuits; more specifically, it relates to a self timing interlock circuit for controlling read, write and page mode write functions of an embedded dynamic random access memory (DRAM).
2. Background of the Invention
The integration of embedded DRAM into specific integrated circuit (ASIC) designs has intensified the focus on architecture, design and test of high performance, high density DRAM in an ASIC environment. The ASIC environment itself presents many difficult challenges that DRAM timings are sensitive to such as noise and voltage and temperature variations as well as fabrication induced device parametric variations. These challenges can only be solved by a robust embedded DRAM architecture that is noise tolerant and can operate at high voltage for performance and low voltage for reduced power consumption.
Additionally, for test throughput, it is desirable that embedded DRAMs be tested with timings that may be optimized for logic circuits but not for DRAMs, making it difficult to identify marginal DRAM cells without unnecessarily impacting yield and thus cost.
Therefore, there is a need in the industry for improved embedded DRAM designs wherein the DRAM timing is less sensitive to noise and voltage, temperature variations.
A first aspect of the present invention is an embedded DRAM comprising: a primary DRAM array comprising: a data cell coupled to a first bitline and coupled to a wordline; a reference cell coupled to the first bitline and coupled to a reference wordline; a first bitline restore circuit coupled to the first bitline and responsive to a first control signal; a first sense amplifier coupled to the first bitline and responsive to a second control signal; and a first column select device for gating writing and reading of the first bitline, the first column select device coupled to the first bitline and responsive to a third control signal; and an extension DRAM array comprising: a dummy cell coupled to a second bitline; a first detector cell coupled to the second bitline and coupled to the reference wordline; a signal development interlock circuit for monitoring the state of the first detector cell and interlocking the second control signal in order to delay the setting of the first sense amplifier until the data cell charges the first bitline; a second detector cell coupled to the second bitline; a write back interlock circuit for monitoring the state of the second detector cell and for delaying turning off the wordline until the data cell is charged; a second bitline restore circuit coupled to the second bitline and responsive to the first control signal; a second sense amplifier coupled to the second bitline and responsive to the second control signal; a sense amplifier interlock circuit for monitoring the state of the second bitline and for delaying the third control signal until the first sense amplifier has stabilized; and a second column select device for gating coupling of the second bitline to a dummy load, the second column select device coupled to the second bitline and responsive to the third control signal.
A second aspect of the present invention is a circuit comprising: a primary DRAM array comprising a data cell coupled to a first bitline and coupled to a wordline, a reference cell coupled to the first bitline and coupled to a reference wordline, a first bitline restore circuit coupled to the first bitline and responsive to a first control signal, a first sense amplifier coupled to the first bitline and responsive to a second control signal and a first column select device for gating data write and read of the first bitline, the first column select device coupled to the first bitline and responsive to a third control signal; an extension DRAM array comprising a dummy cell coupled to a second bitline, a first detector cell coupled to the second bitline and coupled to the reference wordline, the first detector cell generating a signal development control signal, a second detector cell coupled to the second bitline, the second detector cell generating a write back control signal, a second bitline restore circuit coupled to the second bitline and responsive to the first control signal, a second sense amplifier coupled to the second bitline and responsive to the second control signal and a second column select device for gating coupling of the second bitline to a dummy load, the second column select device coupled to the second bitline and responsive to the third control signal; a signal development interlock circuit for generating the second control signal, the signal development interlock circuit coupled to the first detector cell and receiving the signal development control signal; a sense amplifier interlock circuit for generating the third control signal, the sense amplifier interlock circuit coupled to the first control signal and the second bitline; and a write back interlock circuit for controlling turn off of the wordline, the write back interlock circuit coupled to the second detector cell and receiving the write back control signal.
A third aspect of the present invention is a method for self timing a DRAM circuit comprising: providing a primary-DRAM array, the primary DRAM comprising a data cell coupled to a first bitline and coupled to a wordline, a reference cell coupled to the first bitline and coupled to a reference wordline, a first bitline restore circuit coupled to the first bitline and responsive to a first control signal, a first sense amplifier coupled to the first bitline and responsive to a second control signal and a first column select device coupled to the first bitline and responsive to a third control signal, the first column select device gating data write and read of the first bitline; providing an extension DRAM array, the extension array comprising a dummy cell coupled to a second bitline, a first detector cell coupled to the second bitline and coupled to the reference wordline, the first detector cell generating a signal development control signal, a second detector cell coupled to the second bitline, the second detector cell generating a write back control signal, a second bitline restore circuit coupled to the second bitline and responsive to the first control signal, a second sense amplifier coupled to the second bitline and responsive to the second control signal and a second column select device coupled to the second bitline and responsive to the third control signal, the second column select device gating coupling of the second bitline to a dummy load; providing a signal development interlock circuit, the signal development interlock circuit coupled to the first detector cell and receiving the signal development control signal and generating the second control signal; providing a sense amplifier interlock circuit, the sense amplifier interlock circuit coupled to the first control signal and the second bitline and generating the third control signal; and providing a write back interlock circuit, the write back interlock circuit coupled to the second detector cell and receiving the write back control signal and controlling turn off of the wordline.